## Dimitrios Kagaris

### Professor, Ph.D. Dartmouth College, 1994

**Office:** Engineering E-117

**Office Hours:** TWR: 12-2PM, or by appointment

**Phone:** (618) 453-7973

**Email: **kagaris@engr.siu.edu

Dr. Kagaris' research interests are in: (a) digital design automation, (b) design for testability, (c) sensor networks, and (d) data mining and bioinformatics. He is currently serving as an Associate Editor of the IEEE Transactions on Computers.

**Areas of Interest:** VLSI design automation, digital circuit testing, communication networks, data mining.

### Education

- Ph.D. in Computer Engineering, 1994

Dartmouth College, Hanover, New Hampshire. - M.S. in Computer Engineering, 1991

Dartmouth College, Hanover, New Hampshire. - Diploma in Computer Engineering and Informatics, 1988

University of Patras, Patras, Greece.

### Research Interests

- Computer-Aided Design for VLSI Digital Circuits
- Design for Testability, Test Pattern Generation, Built-In Self-Test
- Computer Networks

### Journal Publications

- O. Acevedo, D. Kagaris, "On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation,"
**IEEE Transactions on Computers**, v. 65, n. 2, pp. 664-669, Feb. 2016. - D. Kagaris, "MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, v. 35, n. 1, pp. 114-127, Jan. 2016. - D. Kagaris, C. T. Yiannoutsos, "A Multi-Index ROC-Based Methodology for High Throughput Experiments in Gene Discovery,''
**International Journal of Data Mining and Bioinformatics**, v. 8, n. 1, pp. 42-65, 2013. - D. Kagaris, "Maximizing the Lifetime of a Wireless Sensor Network with Fixed Targets,''
**Ad Hoc and Sensor Wireless Networks**, v. 17, n. 3-4, pp. 253 - 268, 2013. - D. Nikolos, D. Kagaris, S. Sudireddy, S. Gidaros, "An Improved Search Method for Accumulator-Based Test Set Embedding,''
**IEEE Transactions on Computers**, v. 58, n. 1, pp. 132-138, Jan. 2009. - J. Kakade, D. Kagaris, D.K. Pradhan, "Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs,''
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, v. 27, n. 9, pp. 1689-1692, Sept. 2008. - J. Kakade, D. Kagaris, "Minimization of Linear Dependencies through the Use of Phase Shifters,''
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, v. 26, n. 10, pp. 1877-1882, Oct. 2007. - D. Kagaris, T. Haniotakis, "A Methodology for Transistor-Efficient Supergate Design,"
**IEEE Transactions on VLSI Systems**, v. 15, n. 4, pp. 488-492, Apr. 2007. - D. Kagaris, "Improved TDM Switching Assignments for Variable and Fixed Burst Length,"
**International Journal of Satellite Communications and Networking**, v. 25, pp. 93-107, 2007. - D. Kagaris, P. Karpodinis, D. Nikolos, "A Method for Accumulator-Based Test-per-Scan BIST,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, v. 25, n. 11, pp. 2578-2586, Nov. 2006. - D. Kagaris, "A Similarity Transform for Linear Finite State Machines,"
**Discrete Applied Mathematics**, vol. 154, pp. 1570-1577, 2006. - D. Kagaris, R. Aakuthota, A. Verma, "Maximum Sequence Test Pattern Generators with Irreducible Characteristic Polynomials,"
**Microprocessors and Microsystems**, v. 30, n. 2, pp. 117-123, Mar. 2006. - D. Kagaris, S. Tragoudas, S. Kuriakose, "InTeRail: A Test Architecture for Core-Based SOCs,"
**IEEE Transactions on Computers**, v. 55, n. 2, pp. 137-149, Feb. 2006. - D. Mehta, D. Kagaris, R. Viswanathan, "Throughput Performance of an Adaptive ARQ Scheme in Rayleigh Fading Channels,"
**IEEE Transactions on Wireless Communications**, v. 5, n. 1, pp. 12-15, Jan. 2006. - D. Kagaris, "Phase Shifter Merging,"
**Journal of Electronic Testing: Theory and Applications**, vol. 21, no. 2, pp. 161-168, April 2005. - D. Kagaris, "A Unified Method for Phase Shifter Computation,"
**ACM Transactions on Design Automation of Electronic Systems**, vol. 10, no. 1, pp. 157-167, Jan. 2005. - D. Kagaris, "Multiple-Seed TPG Structures,"
**IEEE Transactions on Computers**, vol. 52, no. 12, pp. 1633-1639, Dec. 2003. - D. Kagaris, "On Minimum Delay Clustering Without Replication,"
**Integration, the VLSI Journal**, vol. 36, no.1, pp. 27-39, Sep. 2003. - D. Kagaris, S. Tragoudas, "LFSR Characteristic Polynomials for Pseudoexhaustive TPG with Low Number of Seeds,"
**Journal of Electronic Testing: Theory and Applications**, vol. 19, no. 3, pp. 233--244, June 2003. - D. Kagaris, S. Tragoudas, "On the Non-Emumerative Path Fault Simulation Problem,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 21, no. 9, pp.1095-1100, Sep. 2002. - D. Kagaris, "Linear Dependencies in Extended LFSMs,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 21, no. 7, pp. 852-858, July 2002. - D. Kagaris, S. Tragoudas, "Using a WLFSR to Embed Test Pattern Pairs in Minimum Time,"
**Journal of Electrical Testing: Theory and Applications**, vol. 18, no. 3, pp. 305-313, June 2002. - D. Kagaris, S. Tragoudas, "Von Neumann Hybrid Cellular Automata for Generating Deterministic Test Sequences,"
**ACM Transactions on Design Automation of Electronic Systems**, vol. 6, no. 3, pp. 308-321, 2001. - D. Kagaris, S. Tragoudas, "Computational Analysis of Counter-Based Schemes for VLSI Test Pattern Generation,"
**Discrete Applied Mathematics**, vol. 110, pp. 227-250, 2001. - D. Kagaris, S. Tragoudas, A. Majumdar, "Test-Set Partitioning for Multi-Weighted Random LFSRs,"
**Integration, the VLSI Journal**, vol. 30, pp. 65-75, 2000. - D. Kagaris, S. Tragoudas, "On the Design of Optimal Counter-Based Schemes for Test Set Embedding,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 18, no. 2, pp. 219-230, 1999. - D. Kagaris, S. Tragoudas, "Maximum Weighted Independent Sets on Transitive Graphs and Applications,"
**Integration, the VLSI Journal**, vol. 27, pp. 77-86, 1999. - D. Kagaris, G. E. Pantziou, S. Tragoudas, C. D. Zaroliagis, "On the Computation of Fast Data Transmissions in Networks with Capacities and Delays,"
**Networks**, 33:(3), 167-174, 1999. - D. Kagaris, "A Routing Algorithm for Row-Based FPGAs"
**Microprocessors and Microsystems**, vol. 20, no. 7, pp. 401-407, 1997. - D. Kagaris, S. Tragoudas, D. Karayiannis, "Improved Nonenumerative Path Delay Fault Coverage Estimation based on Optimal Polynomial-Time Algorithms,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 16, no. 3, pp. 309-315, 1997. - D. Kagaris, S. Tragoudas, A. Majumdar, "On the Use of Counters for Deterministic Test Pattern Generation,"
**IEEE Transactions on Computers**, vol. 45, no. 12, pp. 1405-1419, 1996. - D. Kagaris, S. Tragoudas, "A Fast Algorithm for Minimizing FPGA Combinational and Sequential Modules,"
**ACM Transactions on Design Automation of Electronic Systems**, vol. 1, no. 3, pp. 341-351, 1996. - D. Kagaris, S. Tragoudas, "Retiming--Based Partial Scan,"
**IEEE Transactions on Computers**, vol. 45, no. 1, pp. 74-87, 1996. - D. Kagaris, S. Tragoudas, D. Bhatia, "Pseudo-Exhaustive Built-In TPG for Sequential Circuits,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 14, no 9, pp.1160-1171, 1995. - D. Kagaris, S. Tragoudas, "Avoiding Linear Dependencies in LFSR Test Pattern Generators,"
**Journal of Electronic Testing: Theory and Applications**, vol. 6, pp. 229-241, 1995. - D. Kagaris, F. Makedon, S. Tragoudas, "A Method for Pseudo-Exhaustive Test Pattern Generation,"
**IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems**, vol. 13, no. 9, pp. 1170-1178, 1994. - D. Kagaris, S. Tragoudas, "Cost-Effective LFSR Synthesis for Optimal Pseudo-Exhaustive BIST Test Sets,"
**IEEE Transactions on VLSI Systems**, vol. 4, no. 1, pp. 526-536, 1993.

### Peer-Reviewed Conference Publications

- O. Acevedo, D. Kagaris, K. Poluri, H. Ramaprasad, S. Warner, "Towards Optimal Design of Avionics Networking Infrastructures,"
**Proceedings of the 31st Digital Avionics Systems Conference (DASC)**, Oct. 2012, pp. 7A3-1 -- 7A3-13. - O. Acevedo, D. Kagaris, "Using the Berlekamp-Massey Algorithm to Obtain LFSR Characteristic Polynomials for TPG,''
**IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology System**s, Oct. 2012, pp. 233-238. - S. Udar, D. Kagaris, "Minimizing Observation Points for Fault Location,''
**IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems**, Oct. 2009, pp. 263-267. - S. Sudireddy, J. Kakade, D. Kagaris, ``Deterministic Built-in TPG with Segmented FSMs,''
**IEEE International On-Line Testing Symposium**, July 2008, pp. 261-266. - S. Udar, D. Kagaris, "LFSR Reseeding with Irreducible Polynomials,"
**IEEE International On-Line Testing Symposium**, July 2007, pp. 293-298. - C. Jenkins, J. Kakade, D. Kagaris, "Cellular Automata with Large Channel Separations,"
**IEEE International Symposium on Circuits and Systems**, May 2007, pp. 1033-1036. - A. Pillai, W. Zhang, D. Kagaris, "Detecting VLIW Hard Errors Cost-Effectively Through a Software-Based Approach,"
**IEEE International Symposium on Embedded Computing/ IEEE International Conference on Advanced Information Networking and Applications**, May 2007, pp. 811-815. - D. Kagaris, T. Haniotakis, "Transistor-Level Synthesis for Low-Power Applications,"
**IEEE International Symposium on Quality Electronic Design**, Mar. 2007, pp. 607-612. - D. Nikolos, D. Kagaris, S. Gidaros, "Diophantine-Equation Based Arithmetic Test Set Embedding,"
**IEEE International On-Line Testing Symposium**, July 2006, pp. 194-195. - J. Kakade, D. Kagaris, "Phase Shifts and Linear Dependencies,"
**IEEE International Symposium on Circuits and Systems**, May 2006, pp. 1595-1598. - D. Kagaris, T. Haniotakis, "Transistor-Level Optimization of Supergates,"
**IEEE International Symposium on Quality Electronic Design**, Mar. 2006, pp. 682-687. - S. Chidambaram, D. Kagaris, D. K. Pradhan, "A Comparative Study of CA with Phase Shifters and GLFSRs,"
**IEEE International Test Conference**, Nov. 2005, pp. 926-935. - D. K. Pradhan, D. Kagaris, R. Gambhir, "A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage,"
**IEEE International On-Line Testing Symposium**, July 2005, pp. 221-226. - A. Mehta, D. Kagaris, R. Viswanathan, "Throughput Performance of an Adaptive ARQ Scheme in Rayleigh Fading Channels,"
**Conference on Information Sciences and Systems (CISS)**, March 2005. - P. Karpodinis, D. Kagaris, D. Nikolos, "Accumulator based Test-per-Scan BIST,"
**IEEE On-Line Testing Symposium**, July 2004, pp. 193-198. - M. Bellos, X. Kavousianos, D. Nikolos, D. Kagaris, "DV-TSE: Difference Vector Based Test Set Embedding, "
**IFIP International Conference on VLSI-SOC**, Dec. 2003, pp. 343-348. - D. Kagaris, S. Tragoudas, "InTeRail: Using existing and extra interconnects to test core-based SOCs, "
**IEEE On-Line Testing Symposium,**July 2003, pp. 219-224. - D. Kagaris, "Built-In TPG with Designed Phaseshifts, "
**IEEE VLSI Test Symposium**, Apr. 2003, pp. 365-370. - M. Bellos, D. Kagaris, D. Nikolos, "Low Power Test Set Embedding Based on Phase Shifters, "
**IEEE Computer Society Annual Symposium on VLSI**, Feb. 2003, pp. 155-160. - M. Bellos, D. Kagaris, D. Nikolos, "Test Set Embedding Based on Phase Shifters, "
**European Dependable Computing Conference**, Oct. 2002, LNCS 2485, Springer-Verlag, pp. 90-101. - D. Kagaris, "Built-in Generation of m-Sequences with Irreducible Characteristic Polynomials, "
**IEEE International On-Line Testing Workshop,**July 2002, pp. 158-162. - D. Kagaris, S. Tragoudas, "Using a WLFSR to Embed Test Pattern Pairs in Minimum Time, "
**IEEE International On-Line Testing Workshop,**July 2001, pp. 75-79. - D. Kagaris, S. Tragoudas, "Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds, "
**IEEE International Conference on Computer Design**, Sep. 2000, pp. 42-47. - D. Kagaris, S. Tragoudas, "Methods for On-Chip Embedding of Path Delay Test Vectors, "
**Proc. IEEE International Symposium on Circuits and Systems**, May 2000, vol. I, pp. 84-87. - D. Kagaris, S. Tragoudas, "LFSR/SR Pseudoexhaustive TPG in Fewer Test Cycles, "
**IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems**, Nov. 1999, pp. 130-138. - D. Kagaris, S. Tragoudas, "Embedded Cores Using Built-In Mechanisms,"
**IEEE International Symposium on Circuits and Systems**, June 1999, vol. I, pp. 23-26. - D. Kagaris, S. Tragoudas, "Maximum Independent Sets on Transitive Graphs and Their Applications in Testing and CAD,"
**IEEE/ACM International Conference on Computer-Aided Design**, Nov. 1997, pp. 736-740. - D. Kagaris, S. Tragoudas, D. Karayiannis, "Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms,"
**IEEE International Conference on Computer Design**, Oct. 1997, pp. 366-371 (ICCD'97 Oustanding Paper Award). - D. Kagaris, S. Tragoudas, "Cellular Automata for Generating Deterministic Test Sequences,"
**IEEE European Design and Test Conference**, Mar. 1997, pp. 77-81. - D. Kagaris, S. Tragoudas, "A Multiseed Counter TPG with Performance Guarantee,"
**IEEE International Conference on Computer Design**, Oct. 1996, pp. 34-39. - D. Kagaris, S. Tragoudas, "FPGA Module Minimization,"
**IEEE International Conference on Computer Design**, Oct. 1996, pp. 566-570. - D. Kagaris, S. Tragoudas, "Generating Deterministic Unordered Test Patterns with Counters,"
**IEEE VLSI Test Symposium**, Apr. 1996, pp. 374-379. - D. Kagaris, S. Tragoudas, A. Majumdar, "Deterministic Test Pattern Reproduction by a Counter,"
**IEEE European Design and Test Conference**, Mar. 1996, pp. 37-41. - D. Kagaris, G. E. Pantziou, S. Tragoudas, C. D. Zaroliagis, "On the Computation of Fast Data Transmissions in Networks with Capacities and Delays,"
**Workshop on Algorithms and Data Structures**, Aug. 1995, Springer-Verlag LNCS 955, pp. 291-302. - D. Kagaris, G. E. Pantziou, S. Tragoudas, C. D. Zaroliagis, "Quickest Paths: Parallelization and Dynamization,"
**IEEE International Conference on System Sciences**, Jan. 1995, Vol. II, pp. 39-40. - D. Kagaris, S. Tragoudas, "A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators,"
**IEEE International Conference on Computer Design**, Oct. 1994, pp. 292-295 (ICCD'94 Oustanding Paper Award). - D. Kagaris, S. Tragoudas, "A Design for Testability Technique for Test Pattern Generation with LFSRs,"
**IEEE VLSI Test Symposium**, Apr. 1994, pp. 68-73. - D. Kagaris, S. Tragoudas, "Retiming Algorithms with Application to VLSI Testability,"
**IEEE Great Lakes Symposium on VLSI**, Mar. 1994, pp. 216-221. - D. Kagaris, S. Tragoudas, D. Bhatia, "Pseudo-Exhaustive BIST for Sequential Circuits,"
**IEEE International Conference on Computer Design**, Oct. 1993, pp. 523-527. - D. Kagaris, S. Tragoudas, "Partial Scan with Retiming,"
**ACM/IEEE Design Automation Conference**, June 1993, pp. 249-254. - D. Kagaris, F. Makedon, S. Tragoudas, "On Minimizing Hardware Overhead for Pseudo-Exhaustive Circuit Testability,"
**IEEE International Conference on Computer Design**, Oct. 1992, pp. 358-364. - D. Kagaris, F. Makedon, S. Tragoudas, "A Metric towards Efficient Pseudo-Exhaustive Test Pattern Generation,"
**IEEE International Symposium on Circuits and Systems**, May 1992, pp. 379-382.

### Awards

- National Science Foundation (NSF) grant CCR-9815229 for the proposal entitled "Built-in Test Mechanisms and Embedded Cores," (with S. Tragoudas). Total Amount: $255,829.00. Duration: Aug. 1998-May 2001.
- Outstanding Paper Award in IEEE International Conference on Computer Design 1997 (ICCD'97) for the paper "Nonenumerative Path Delay Fault Coverage Estimation with Optimal Polynomial-Time Algorithms,"
**Proc. IEEE International Conference on Computer Design**, Oct. 1997, pp. 366-371. - Outstanding Paper Award in IEEE International Conference on Computer Design 1994 (ICCD'94) for the paper "A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators,"
**Proc. IEEE International Conference on Computer Design**, Oct. 1994, pp. 292-295.