Cadence Univeristy Program Member
 |
 |
Adjust cdsSpice Tolerances for Convergence During Simulation
FOR ECE423 ‘7-SEGMENT DISPLAY’ LAB
In case your cdsSpice simulation terminates before the designated time instant, you may need to adjust the settings on the simulator.
Go to ADE -> Simulation -> Options -> Analog and get the following window open:
Change ABSTOL, CHGTOL & RELTOL to 1e-6, 1e-7 & 1e-2 respectively. Click OK and re-run the simulation.
Disclaimer: Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorshiop, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this inormation within your environment.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134