Chao Lu | ECE | SIU

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Southern Illinois University

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SIU.EDU

Electrical and Computer Engineering

College of Engineering

Chao Lu

Assistant Professor, Ph.D. Purdue University, 2012

Chao Lu

Office: Engineering E-223

Office Hours: MWF: 1-3PM, or by appointment

Phone: (618) 453-7028

Email: chaolu@siu.edu

Lab: VLSI System Research

Website

Dr. Lu's research interests include (a) HEVC/H.265 real-time video encoding algorithms and VLSI hardware architecture, and (b) Deep neural network algorithm and VLSI hardware architecture (for smart building, self-driving, pattern recognition, and video/image processing applications).

Open Positions

I have opening positions in my VLSI system research lab for PhD students on exciting projects with funding support. Please contact me with your complete resume if you are interested in working together with me.​

Teaching

  ECE 327 Digital Circuit Design with HDL

  ECE 426/516 Implementation of VLSI Systems with HDL

  ECE 515 Three Dimensional Integration Systems

Education

Purdue University, West Lafayette, IN Ph.D. Electrical and Comp. Engineering 12/12

Hong Kong Univ. of Science & Technology M. Eng. Electrical and Comp. Engineering 07/07

Nankai University, Tianjin, China B. Eng. Microelectronics 05/04

Working Experience

08/15-Present  Assistant Professor, Department of Electrical and Computer Engineering

09/14-08/15 3D IC Chip Designer, Tezzaron Semiconductor, IL, 60563

01/13-09/14 R&D Circuit Design Engineer, Arctic Sand Technologies, Cambridge, MA

08/08-12/12 Research Assistant, Department of Electrical and Computer Engineering

05/11-08/11 Intern Engineer, Silicon Laboratories Inc., Sunnyvale, CA, 94085

08/05-08/07 Research Assistant, Department of Electrical and Computer Engineering

08/04-08/05 Teaching Assistant, Department of Electrical and Computer Engineering

Technical Expertise

Research and develop cutting-edge IC technology/circuit/platform.

Architect, design and verify circuits from schematic through layout.

Assist in develop and implement test circuit and test plan.

Prototype chip testing to validate analog circuit and system performance.

Professional Service

Technical Program Committee of ACM International Symposium on Low-Power Electronics and Design (2015), IEEE/ACM Great Lake Symposium on VLSI (2011-2014)

Editorial Board Member of International Journal of Electronics and Communications, Elsevier, 2012-Present

Journal Referee

◦ IEEE Journal of Solid-State Circuits (JSSC)

◦ IEEE Transactions on Very Large Scale Integration (VLSI) Systems

◦ IEEE Transactions on Circuits and Systems I (TCAS-I)

◦ IEEE Transactions on Circuits and Systems II (TCAS-II)

Recent Publications

Huachao Xu, Yuanzhi Zhang, Chao Lu, Guofeng Li, "A 0.45 ppm analog temperature compensated crystal oscilator using novel compensation algorithm and network", International Journal of Electronics and Communications, vol. 90, pp. 69-78, June 2018.

Yuanzhi Zhang, Chao Lu, "A Highly-Parallel Hardware Architecture of Table-based CABAC Bit Rate Estimator in HEVC Intra Encoder", IEEE Transactions on Circuits and Systems for Video Technology, accepted, 2018.

Xiaoqiang Li, Ruifeng Liu, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu, "A 5.7~6 GHz CMOS PLL with low phase noise and -68dBc reference spur", International Journal of Electronics and Communications, vol. 85, pp. 23-31, 2018.

Meijuan Zhang, Ruifeng Liu, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu, "A fully Integrated RSSI and ultra low power ADC for 5.8 GHz DSRC China ETC transceiver", International Journal of Electronics and Communications, vol. 86, pp. 154-163, 2018.

Baolin Wei, Chao Lu, "Transition Metal Dichalcogenide MoS2 Field-Effect Transistors for Analog Circuits: A Simulation Study", International Journal of Electronics and Communications, vol. 88, pp. 110-119, 2018.

Linglig Cao, Ruifeng Liu, Yuanzhi Zhang, Meijuan Zhang, Xiaoqiang Li, Wenshen Wang, Huimin Liu, Chao Lu, "A 5.8GHz Digitally Controlled DSRC CMOS Receiver with A Wide Dyanmic Range for Chinese ETC System", IEEE Transactions on Circuits and Systems II, accepted, 2018.

Yan, H. Wang, Z. Zhang, C. Ho, H. He, C. Lu, X. Jia, Y. Zhang, T. Yang, J. Zhao, Z. Zhou, M. Zhao, "A graphene oxide quantum dots embedded charge trapping memory with enhanced memory window and data retention", IEEE Journal of the Electron Devices Society, vol. 6, pp. 464-467, 2018.

Yuanyuan Zhang, Tao Yang, Xiaobing Yan, Zichang Zhang, Gang bai, Chao Lu, Xinlei Jia, Bangfu Ding, Jianhu Zhao, and Zhenyu Zhou, "A Metal/Ba0.6Sr0.4TiO3/SiO2/Si Single Film Device for Charge Trapping Memory Towards a Large Memory Window", Applied Physics Letter, 110, 223501, 2017.

Chih-Hisang Ho, Dung-Sheng Tsai, Chao Lu, Sooyoun Kim, Selin Mungan, Yuanzhi Zhang, Jr-Hau He, "Device Process and Circuit Application Interaction for Harsh Electronics: Radiation-Hardening Hf-In-Zn-O Thin Film Transistors as an Example", IEEE Electron Device Letters, vol. 38, no. 8, pp. 1039-1042, August, 2017.

Sizhao Li,  Yuanzhi Zhang, Yan Chen, Chao Lu, Donghui Guo, "Race-Condition-Aware Task Partitioning and Scheduling Using Entropy Maximization", IEEE Transactions on Parallel and Distributed Systems, accepted, 2017.

Min Chen, Yuanzhi Zhang*, Chao Lu, "Efficient Architecture of Variable Size HEVC 2D-DCT for FPGA Platforms", International Journal of Electronics and Communications, in press, 2017.

S. Baytok, C. Lu, C. H. Ho, V. Raghunathan, K. Roy, “Effects of Deposition Process on Poly-Si Micro-scale Energy Scavenging Systems”, IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1650-1657, April, 2016.

X. Wang, C. Lu, Z. Mao, "Power efficient SRAM design with integrated bit line charge pump", International Journal of Electronics and Communications, vol. 70, no. 10, pp. 1395-1402, 2016.

X. Wang, C. Lu, Z. Mao, “Charge recycling 8T SRAM design for low voltage robust operation”, International Journal of Electronics and Communications, 2015.volume 70, issue 1, pp. 25-32, January, 2016.

C. H. Ho, C. Lu, K. Roy, “An enhanced voltage programming pixel circuit for compensating brightness variation in AMOLED displays”, IEEE Journal of Display Technology, vol. 10, issue 5, pp. 345-351, January, 2014.

C. Lu, C. Y. Tsui, W. H. Ki, “Vibration energy scavenging system with maximum power tracking for micro power applications“, IEEE Transactions on VLSI Systems, vol. 19, issue 11, pp. 2109-2119, November, 2011.

C. Lu, V. Raghunathan, K. Roy, “Efficient design of micro-scale energy harvesting systems”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, issue 3, pp. 254-266, September, 2011. 

C. W. Lin, C. H. Ho, C. Lu, D. Fang and K. Roy, “A process/device/circuit/system compatible simulation framework for poly-Si TFT based SRAM design”, SISPAD, 2013.

S. H. Choday, C. Lu, V. Raghunathan, K. Roy, ”On-chip energy harvesting using thin-film thermoelectric materials”, Semi-Therm, 2013.

C. H. Ho, G. D. Panagopoulos, C. Lu, K. Roy, “A physical model to predict the vth variation of poly-si TFTs induced by grain boundaries”, SISPAD, 2012.

S. Baytok, C. Lu, K. Roy, V. Raghunathan, “Modeling, design and cross-layer optimization of polysilicion solar cell based micro-scale energy harvesting system”, ISLPED, 2012.

C. Lu, S. P. Park, V. Raghunathan, K. Roy, “Low overhead maximum power point tracking for micro-scale solar energy harvesting systems”, VLSI Design, 2012.

C. Lu, V. Raghunathan, K. Roy, “Maximum power point considerations for micro-scale solar energy harvesting systems”, ISCAS, 2010. (Invited)

C. Lu, V. Raghunathan, K. Roy, “Micro-scale energy harvesting: a system perspective”, ASPDACP, 2010. (Invited)

C. Lu, C. Y. Tsui, W. H. Ki, “Vibration energy scavenging and management for ultra-low power Applications”, ISLPED, 2007. (Best Paper Award, 2 out of 192 submissions, 1%)